1. Field of Invention
The present invention relates to a multi-chip stack package. More particularly, the present invention relates to a multi-chip stack package and a fabricating method thereof, wherein the quality of a multi-chip stack package is improved.
2. Description of Related Art
As electronic technology continues to advance, more personalized, multi-functional high-tech electronic products are being introduced into the market. The newer electronic products are characteristically smaller, lighter and slimmer. As a result, the products occupy less space and are more portable. In the semiconductor manufacturing, many types of packages now incorporate a multi-chip concept so that volume occupation of an integrated circuit is reduced and electrical performance is improved. In a multi-chip stack package, few chips are stacked over each other and enclosed inside the package so that horizontal sectional area of the package is greatly reduced.
FIG. 1 is a cross-sectional view of a conventional multi-chip stack package. To fabricate a multi-chip stack package, a first chip 110 having a first active surface 112 and a first chip back surface 114 is provided. The first chip 110 further includes a plurality of first bonding pads 116 positioned over the active surface 112. A substrate 120 having a substrate surface 122 is also provided. The substrate 120 has a plurality of first contacts 124 and a plurality of second contacts 126 on the substrate surface 122. The first chip 110 and the substrate 120 are joined together using a conventional flip chip method. First, a plurality of bumps 130 are formed over the first bonding pads 116 of the first chip 110. Thereafter, the first chip 110 is positioned over the substrate 120 such that each bump 130 is aligned with a corresponding first contact 124 on the substrate surface 122. A reflow process is conducted so that the bumps 130 and the first contacts 124 are bonded together. Afterwards, filler material 132 is injected into the space between the chip 110 and the substrate 120 so that the filler material 132 encloses the bumps 130. A second chip 140 having a second active surface 142 and corresponding second chip back surface 144 is provided. The second chip 140 further includes a plurality of second bonding pads 146 positioned on the second active surface 142. Through adhesive glue 150, the second chip back surface 144 of the second chip 140 is attached to the first chip back surface 114. A wire-bonding operation is conducted to form a plurality of conductive wires 152 with one end bonded to the second bonding pads 146 of the second chip 140 and the other end bonded to the second contacts 126 on the substrate 120. Finally, the first chip 110, the second chip 140 and the conductive wires 152 are encapsulated by injecting packaging glue 150 in a molding process.
In the aforementioned fabrication process, the adhesive glue 150 is spread over the first chip back surface 114 before attaching the second chip 140 onto the first chip back surface 114 in the process of joining the first chip 110 and the second chip 140. However, when excessive attaching pressure is applied to the second chip 140, some adhesive material 150 may bleed out. In other words, some of the adhesive glue 150 may be forced out from the attachment region of the second chip 140. In some cases, the adhesive glue 150 may ‘climb’ to the second active surface 142, and hence affecting the wire-bonding operation. If the adhesive glue 150 creeps into the second bonding pad 146 surface, the conductive wire 152 is no longer able to bond with the second bonding pad 146. In addition, the wire-bonding head (not shown) of the wire-bonding machine (not shown) may also drag up some adhesive material. Ultimately, the quality of electrical connections between the first chip 110 and the second chip 140 is likely to be affected.